Divide and Measure : CFG Segmentation for the Measurement-Based Analysis of Resource Consumption

A computer system is a good computer system if it correctly performs the task it was intended to perform. This is not even half of the truth: Non-functional requirements are abundant in the world of software and system engineering, even if they are not always stated explicitly. In our work we are concerned with the measurement-based analysis of resource consumption. Examples of resources are time, energy, or memory space. In the context of our measurement-based approach for software analysis, we face the problem of breaking the software under examination into smaller parts of managable size, a process dubbed CFG Segmentation

INFER: Interactive Timing Profiles based on Bayesian Networks

We propose an approach for timing analysis of software-based embedded computer systems that builds on the established probabilistic framework of Bayesian networks. We envision an approach where we take (1) an abstract description of the control flow within a piece of software, and (2) a set of run-time traces, which are combined into a Bayesian network that can be seen as an interactive timing profile. The obtained profile can be used by the embedded systems engineer not only to obtain a probabilistic estimate of the WCET, but also to run interactive timing simulations, or to automatically identify software configurations that are likely to evoke noteworthy timing behavior, like, e.g., high variances of execution times, and which are therefore candidates for further inspection

A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip

Nilesh Karavadara, Simon Folie, Michael Zolda, Vu Thien Nga Nguyen, Raimund Kirner, 'A Power-Aware Framework for Executing Streaming Programs on Networks-on-Chip'. Paper presented at the Int'l Workshop on Performance, Power and Predictability of Many-Core Embedded Systems (3PMCES'14), Dresden, Germany, 24-28 March 2014.Software developers are discovering that practices which have successfully served single-core platforms for decades do no longer work for multi-cores. Stream processing is a parallel execution model that is well-suited for architectures with multiple computational elements that are connected by a network. We propose a power-aware streaming execution layer for network-on-chip architectures that addresses the energy constraints of embedded devices. Our proof-of-concept implementation targets the Intel SCC processor, which connects 48 cores via a network-on- chip. We motivate our design decisions and describe the status of our implementation

Calculating WCET Estimates from Timed Traces

© The Author(s) 2015. This article is published with open access at Springerlink.comReal-time systems engineers face a daunting duty: They must ensure that each task in their system can always meet its deadline. To analyse schedulability they must know the worst-case execution time (WCET) of each task. However, determining exact WCETs is practically infeasible in cost-constrained industrial settings involving real-life code and COTS hardware. Static analysis tools that could yield sufficiently tight WCET bounds are often unavailable. As a result, interest in portable analysis approaches like measurement-based timing analysis (MBTA) is growing. We present an approach based on integer linear programming (ILP) for calculating a WCET estimate from a given database of timed execution traces. Unlike previous work, our method specifically aims at reducing overestimation, by means of an automatic classification of code executions into scenarios with differing worst-case behaviour. To ease the integration into existing analysis tool chains, our method is based on the implicit path enumeration technique (IPET). It can thus reuse flow facts from other analysis tools and produces ILP problems that can be solved by off-the-shelf solvers.Peer reviewe

Dynamic Power Management for Reactive Stream Processing on the SCC Tiled Architecture

This article is distributed under the terms of the Creative Commons Attribution 4.0 International License(http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.Dynamic voltage and frequency scaling} (DVFS) is a means to adjust the computing capacity and power consumption of computing systems to the application demands. DVFS is generally useful to provide a compromise between computing demands and power consumption, especially in the areas of resource-constrained computing systems. Many modern processors support some form of DVFS. In this article we focus on the development of an execution framework that provides light-weight DVFS support for reactive stream-processing systems (RSPS). RSPS are a common form of embedded control systems, operating in direct response to inputs from their environment. At the execution framework we focus on support for many-core scheduling for parallel execution of concurrent programs. We provide a DVFS strategy for RSPS that is simple and lightweight, to be used for dynamic adaptation of the power consumption at runtime. The simplicity of the DVFS strategy became possible by sole focus on the application domain of RSPS. The presented DVFS strategy does not require specific assumptions about the message arrival rate or the underlying scheduling method. While DVFS is a very active field, in contrast to most existing research, our approach works also for platforms like many-core processors, where the power settings typically cannot be controlled individually for each computational unit. We also support dynamic scheduling with variable workload. While many research results are provided with simulators, in our approach we present a parallel execution framework with experiments conducted on real hardware, using the SCC many-core processor. The results of our experimental evaluation confirm that our simple DVFS strategy provides potential for significant energy saving on RSPS.Peer reviewe

The WCET Tool Challenge 2011

Following the successful WCET Tool Challenges in 2006 and 2008, the third event in this series was organized in 2011, again with support from the ARTIST DESIGN Network of Excellence. Following the practice established in the previous Challenges, the WCET Tool Challenge 2011 (WCC'11) defined two kinds of problems to be solved by the Challenge participants with their tools, WCET problems, which ask for bounds on the execution time, and flow-analysis problems, which ask for bounds on the number of times certain parts of the code can be executed. The benchmarks to be used in WCC'11 were debie1, PapaBench, and an industrial-strength application from the automotive domain provided by Daimler AG. Two default execution platforms were suggested to the participants, the ARM7 as "simple target'' and the MPC5553/5554 as a "complex target,'' but participants were free to use other platforms as well. Ten tools participated in WCC'11: aiT, Astr\'ee, Bound-T, FORTAS, METAMOC, OTAWA, SWEET, TimeWeaver, TuBound and WCA

Towards Distributed Robustness in Embedded Systems

Final Accepted Versio

Compiler Support for Measurement-based Timing Analysis

Measurement-based timing analysis (MBTA) techniques have been developed as a complimentary to static WCET analysis, in order to exploit worst-case execution time (WCET) analysis at early stages of system development. The direct advantage of MBTA is that, in contrast to static WCET analysis, no timing model of the hardware platform has to be developed. Instead the timing model is generated automatically by performing systematic execution time measurements. MBTA provides high retargetability, as the test suite used for execution time measurements is typically derived from the source code of the program. In order to provide an accurate WCET estimate, the test suite has to provide a sufficient coverage of the temporal system behavior. Here also the compilation tool chain is important as the compiler may introduce additional control flow that is not visible at the source code. In this paper we present FORTAS, an MBTA tool that systematically generates test data using a range of different techniques, like heuristics and model checking. Furthermore, we show how compiler support for MBTA can provide code optimization while preserving the code coverage achieved by the MBTA test suite at source-code level. First evaluations indicate that the performance penalty for ensuring coverage preservation of the test suite is lowFinal Accepted Versio

Let's get less optimistic in measurement-based timing analysis

“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”Measurement-based timing analysis (MBTA) is a hybrid approach that combines execution time measurements with static program analysis techniques to obtain an estimate of the worst-case execution time (WCET) of a program. In order to minimize the chance that the WCET estimate is below the real WCET, the set of representative execution-time measurements has to be selected advisedly. We present an input data generation technique that uses a combination of model checking and genetic algorithms in order to heuristically optimize the set of measurements in terms of safety

Towards Adaptable Control Flow Segmentation for measurement-Based Execution Time Analysis

During the design of embedded real-time systems, engineers have to consider the temporal behavior of software running on a particular hardware platform. Measurement-based timing analysis is a technique that combines elements from static code analysis with execution time measurements on real physical hardware. Because performing exhaustive measurement is generally not tractable, some kind of abstraction must be used to deal with the combinatoric complexity of real software. We propose an adaptable measurement-based analysis approach that uses the novel flexible abstraction of a segment graph to model control flow at varying levels of detail. We also present preliminary experimental results produced by a prototype implementation